This invention relates to a nonvolatile semiconductor memory device such as a NOR-type flash memory and a method for manufacturing the same, and more particularly to the pattern construction of a memory cell array.
FIGS. 1A to 1D show the pattern construction of a memory cell array in a NOR-type flash memory as an example of the conventional nonvolatile semiconductor memory device. FIG. 1A is a pattern plan view, FIG. 1B is a cross sectional view taken along the 1Bxe2x80x941B line of the pattern of FIG. 1A, FIG. 1C is a cross sectional view taken along the 1Cxe2x80x941C line of the pattern of FIG. 1A, and FIG. 1D is a cross sectional view taken along the 1Dxe2x80x941D line of the pattern of FIG. 1A.
As shown in FIGS. 1A to 1D, field oxide films (element isolation regions) 2 are formed on the main surface of a silicon substrate 1 by the LOCOS method. Source and drain regions 3 and 4 are separately formed on the surface areas of the silicon substrate 1 which are separated by the field oxide film 2. Each source region 3 is formed of a pattern which is continuous in the row direction and commonly used by adjacent memory cells (cell transistors). A floating gate 6 is formed above the channel region between the source and drain regions 3 and 4 of each cell transistor with a tunnel oxide film 5 disposed therebetween. A control gate 8 is formed above the floating gate 6 with an insulating film 7 disposed therebetween. Each control gate 8 is formed to extend along the row direction to construct a word line. An inter-level insulating film 9 is formed on the stacked gate structure and bit lines 10 and common source lines 11 are formed on the inter-level insulating film 9 in a column direction which intersects the word lines (control gates) 8. The common source line 11 is connected to the source regions 3 via through holes 13 in source contact portions 12 and the bit line 10 is connected to the drain regions 4 via through holes 14.
In the NOR-type flash memory with the above structure, it is necessary to make contacts between the common source line 11 and the source regions 3 of the cell transistors in the pattern of the memory cell array. In this case, if formation of the through holes 13 in the inter-level insulating film and mask misalignment are taken into consideration, the patterns of the source regions 3 and common source line 11 in the source contact portions 12 must be made large or wide and the field oxide films (element isolation regions) 2 become different in the shape and interval thereof from the other region in the memory cell array. Therefore, the pattern formed when a slit for forming the floating gate 6 is formed becomes different in the interval thereof in the source contact portion 12 and in the memory cell section, and the pattern configuration of the word line 8 becomes different in some cases. As a result, repetitiveness with the regular interval of the pattern of the whole memory cell array is disturbed, and the etching process for forming the slits in this portion or the etching process for forming the word lines cannot be uniformly effected, thereby causing variations in various electrical characteristics for each memory cell thus formed, for example, the erasing characteristic by the F-N (Fowler-Nordheim) current and the programming characteristic by channel hot electrons. If the erasing characteristic is varied, the threshold voltage of the memory cell after erasing becomes negative, thereby causing a cell current to always flow irrespective of the word line potential. Therefore, if one of memory cells lying on the same bit line as the defective cell is selected, an erroneous reading operation may be effected.
As described above, the conventional nonvolatile semiconductor memory device and a method for manufacturing the same have a problem that the etching process becomes non-uniform and various electrical characteristics for each memory cell are varied since a portion in which repetitiveness with the regular interval of the pattern of the memory cell array is disturbed is present.
Accordingly, a first object of this invention is to provide a nonvolatile semiconductor memory device capable of preventing a variation in the etching process due to the disturbance of repetitiveness with the regular interval of the pattern of the memory cell array and making the various electrical characteristics of each memory cell uniform.
A second object of this invention is to provide a method for manufacturing a nonvolatile semiconductor memory device capable of preventing a variation in the etching process due to the disturbance of repetitiveness with the regular interval of the pattern of the memory cell array and making the various electrical characteristics of each memory cell uniform.
The first object of this invention can be attained by a nonvolatile semiconductor memory device having a memory cell array in which nonvolatile memory cells are arranged in an array form on a semiconductor substrate and which has element regions isolated by element isolation regions of STI (Shallow Trench Isolation) structure, wherein the element isolation regions include a plurality of stripe-form trenches regularly arranged with substantially the same width and the same interval in an area from one end to the opposite end of the memory cell array and insulating films filled in the trenches.
With the above construction, since the plurality of trenches which form the element isolation regions of STI structure are formed in a narrow stripe-form configuration with substantially the same width and the same interval and the pattern has the high degree of repetitiveness with the regular interval, occurrence of a variation in the etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
The first object of this invention can be attained by a nonvolatile semiconductor memory device having a memory cell array in which nonvolatile memory cells are arranged in an array form on a semiconductor substrate, wherein each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate between source and drain regions, a floating gate formed on the tunnel insulating film by isolating a silicon layer by use of plurality of stripe-form slits regularly formed with substantially the same width and the same interval in an area from one end to the opposite end of the memory cell array, an insulating film formed on the floating gate, and a control gate formed on the insulating film.
With the above construction, since the plurality of slits which form the floating gate by isolating the silicon layer are formed in a narrow stripe-form configuration with substantially the same width and the same interval and the pattern of the memory cell array has the high degree of repetitiveness with the regular interval, occurrence of a variation in the etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
The first object of this invention can be attained by a nonvolatile semiconductor memory device having a memory cell array in which nonvolatile memory cells are arranged in an array form on a semiconductor substrate, wherein a plurality of stripe-form word lines regularly arranged with substantially the same width and the same interval in an area from one end to the opposite end of the memory cell array are provided.
With the above construction, since the plurality of word lines (control gates) are formed in a narrow stripe-form configuration with substantially the same width and the same interval and the pattern of the memory cell array has the high degree of repetitiveness with the regular interval, occurrence of a variation in the etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
The first object of this invention can be attained by a nonvolatile semiconductor memory device having a memory cell array in which nonvolatile memory cells are arranged in an array form on a semiconductor substrate and which has element regions isolated by element isolation regions of STI (Shallow Trench Isolation) structure, wherein the element isolation regions include a plurality of stripe-form trenches regularly arranged with substantially the same width and the same interval along a first direction from one end to the opposite end of the memory cell array and insulating films filled in the trenches, and each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate between source and drain regions, a floating gate formed on the tunnel insulating film by isolating a silicon layer by use of a plurality of stripe-form slits regularly formed with substantially the same width and the same interval along the first direction from one end to the opposite end of the memory cell array, an insulating film formed on the floating gate, and a control gate formed on the insulating film.
With the above construction, since the plurality of trenches which form the element isolation regions of STI structure are formed in a narrow strip-form configuration with substantially the same width and the same interval, the plurality of slits for forming the floating gate by isolating the silicon layer are formed in a narrow strip-form configuration with substantially the same width and the same interval and the pattern of the memory cell array has the higher degree of repetitiveness with the regular interval, occurrence of a variation in the etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
Further, the first object of this invention can be attained by a nonvolatile semiconductor memory device having a memory cell array in which nonvolatile memory cells are arranged in an array form on a semiconductor substrate and which has element regions isolated by element isolation regions of STI (Shallow Trench Isolation) structure, wherein the element isolation regions include a plurality of stripe-form trenches regularly arranged with substantially the same width and the same interval along a first direction from one end to the opposite end of the memory cell array and insulating films filled in the trenches, each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate between source and drain regions, a floating gate formed on the tunnel insulating film, an insulating film formed on the floating gate, and a control gate formed on the insulating film, and the control gate forms a plurality of stripe-form word lines regularly arranged with substantially the same width and the same interval along a second direction which intersects the first direction from one end to the opposite end of the memory cell array.
With the above construction, since the plurality of trenches which form the element isolation regions of STI structure are formed in a narrow stripe-form configuration with substantially the same width and the same interval and the plurality of word lines (control gates) are formed in a narrow stripe-form configuration with substantially the same width and the same interval, the pattern of the memory cell array has the higher degree of repetitiveness with the regular interval, occurrence of a variation in the etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
The first object of this invention can be attained by a nonvolatile semiconductor memory device having a memory cell array in which nonvolatile memory cells are arranged in an array form on a semiconductor substrate, wherein each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate between source and drain regions, a floating gate formed on the tunnel insulating film by isolating a silicon layer by use of a plurality of stripe-form slits regularly formed with substantially the same width and the same interval along a first direction from one end to the opposite end of the memory cell array, an insulating film formed on the floating gate, and a control gate formed on the insulating film, and the control gates constitute a plurality of stripe-form word lines regularly arranged with substantially the same width and the same interval in a second direction which intersects the first direction from one end to the opposite end of the memory cell array.
With the above construction, since the plurality of stripe-form slits for forming the floating gates by isolating the silicon layer are regularly formed in a narrow stripe-form configuration with substantially the same width and the same interval and the plurality of word lines (control gates) are also formed in a narrow stripe-form configuration with substantially the same width and the same interval, the pattern of the memory cell array has the higher degree of repetitiveness with the regular interval, occurrence of a variation in the etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
The first object of this invention can be attained by a nonvolatile semiconductor memory device having a memory cell array in which nonvolatile memory cells are arranged in an array form on a semiconductor substrate and which has element regions isolated by element isolation regions of STI (Shallow Trench Isolation) structure, wherein the element isolation regions include a plurality of stripe-form trenches regularly arranged with substantially the same width and the same interval in a first direction from one end to the opposite end of the memory cell array and insulating films filled in the trenches, each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate between source and drain regions, a floating gate formed on the tunnel insulating film by isolating a silicon layer by use of a plurality of stripe-form slits regularly formed with substantially the same width and the same interval along the first direction from one end to the opposite end of the memory cell array, an insulating film formed on the floating gate, and a control gate formed on the insulating film, and the control gates constitute a plurality of stripe-form word lines regularly arranged with substantially the same width and the same interval in a second direction which intersects the first direction from one end to the opposite end of the memory cell array.
With the above construction, since the plurality of trenches which form the element isolation regions of STI structure are formed in a narrow stripe-form configuration with substantially the same width and the same interval, the slits for forming the floating gates by isolating the silicon layer are formed in a continuous narrow stripe-form configuration with substantially the same width and the same interval and the plurality of word lines (control gates) are also formed in a narrow stripe-form configuration with substantially the same width and the same interval, the pattern of the memory cell array has the higher degree of repetitiveness with the regular interval, a variation in the etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
The second object of this invention can be attained by a method for manufacturing a nonvolatile semiconductor memory device comprising the steps of forming a plurality of stripe-form trenches arranged with substantially the same width and the same interval in a first direction on the main surface of a semiconductor substrate; forming element isolation regions of STI (Shallow Trench Isolation) structure by filling insulating films in the trenches; forming a tunnel insulating film on element regions of the semiconductor substrate isolated by the element isolation regions; forming a first polysilicon layer on the tunnel insulating film; forming a plurality of stripe-form slits arranged with substantially the same width and the same interval in the first polysilicon layer in the first direction; forming an insulating film on the first polysilicon layer in which the slits are formed; forming a second polysilicon layer on the insulating film; and patterning a stacked structure of the second polysilicon layer, insulating film and first polysilicon layer to form stripe-form patterns with substantially the same width and the same interval in a second direction which intersects the first direction.
With the above manufacturing method, since the plurality of trenches which form the element isolation regions of STI structure are formed in a narrow stripe-form configuration with substantially the same width and the same interval, the plurality of slits used for forming openings in the first polysilicon layer are formed in a narrow stripe-form configuration with substantially the same width and the same interval and the stacked structure of the second polysilicon layer, insulating film and first polysilicon layer is patterned into a plurality of line patterns with substantially the same width and the same interval, the pattern of the memory cell array has the extremely high degree of repetitiveness with the regular interval, occurrence of a variation in each etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
Further, the second object of this invention can be attained by a method for manufacturing a nonvolatile semiconductor memory device comprising the steps of forming a tunnel insulating film on element regions of a semiconductor substrate which are isolated by element isolation regions; forming a first polysilicon layer on the tunnel insulating film; forming a plurality of stripe-form slits arranged with substantially the same width and the same interval in the first polysilicon layer in a first direction; forming an insulating film on the first polysilicon layer in which the slits are formed; forming a second polysilicon layer on the insulating film; and patterning a stacked structure of the second polysilicon layer, insulating film and first polysilicon layer to form stripe-form patterns with substantially the same width and the same interval in a second direction which intersects the first direction.
With the above manufacturing method, since the plurality of slits used for forming the openings in the first polysilicon layer are formed in a narrow stripe-form configuration with substantially the same width and the same interval and the stacked structure of the second polysilicon layer, insulating film and first polysilicon layer is patterned into a plurality of line patterns with substantially the same width and the same interval, the pattern of the memory cell array has the extremely high degree of repetitiveness with the regular interval, occurrence of a variation in each etching process can be prevented and the various electrical characteristics of each memory cell can be made uniform.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.